Negative bias temperature instability (NBTI) is the tendency of a p-type metal oxide semiconductor (PMOS) transistor to degrade in performance when the PMOS transistor is negatively biased at the gate terminal relative to the remaining terminals of the transistor. The degree of NBTI-induced degradation varies in accordance with the amount of the stress voltage, temperature and duration of waveform transitions, the age of the transistors, and characteristics of the transistors being stressed, such as the threshold voltage and drive current, over a period of time. NBTI can increase the required threshold voltage of the transistor gate and decrease the drive current of the transistor. As a result, NBTI is a reliability concern in circuit based technologies that utilize PMOS transistors, such as advanced complementary metal oxide semiconductor (CMOS) technology.
NBTI is also a concern when managing long-term parameter drifts for comparators and other similar electronic devices that include one or more PMOS input pairs. In particular to comparators used to monitor voltage levels, if the PMOS input pair is not working under substantially similar operating conditions for a period of time, the electronic devices will experience a parameter drift at the two different PMOS inputs. The input offset voltage for the electronic device could continue to drift higher as the device continues to operate. For instance, the input offset voltage for a comparator can drift as high as tens of millivolts (mV) or even hundreds of mV depending on different process technology and/or inherent device properties. If large enough, the input offset voltage may cause the long-term parameters to drift out of the device's operating specification. To compound the problem, long-term parameter drifts are difficult to detect during automatic test equipment (ATE) testing and/or simulation checks. As such, minimizing long-term parameter drifts from NBTI for electronic devices, such as comparators that monitors voltage levels, remain valuable in improving the performance of the electronic devices with PMOS inputs.